The subject application is related to subject matter disclosed in Japanese Patent Application No. H2000-65409 filed on Mar. 9, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
The present invention relates generally to a buffer circuit for selectively driving a plurality of gate circuits scattered in a semiconductor integrated circuit, and a semiconductor device and semiconductor memory device including the same.
When a plurality of gate electrodes scattered in a semiconductor chip are selectively driven by a single buffer circuit, the drivability of the buffer circuit is determined by a balance between the signal propagation delay and consumed current value in a path having the maximum signal propagation delay. That is, although the driving current for the buffer circuit must be increased in order to decrease the signal propagation delay, it is usually required to design the buffer circuit so that the operating frequency of the buffer circuit is not less than a target operating frequency and the consumed current value exceeds a specified value.
FIG. 14 is a schematic diagram of a conventional semiconductor memory device including a buffer circuit of this type.
A memory cell array 1 comprising memory cells (not shown) arranged in the form of an array is divided into eight sections SEC0 through SEC7. Input data DATA less than 0 greater than  to be written in the memory cells are transferred to a global data line 3 by means of a global write buffer 2. On the other hand, each of signals SEC less than 0:7 greater than  for selecting a section, in which data are to be written and which is obtained by decoding upper three bits of an address, is designed to activate one of local write buffers 4, each of which is provided for a corresponding one of the sections. Data transferred to the global data line 3 are written in the memory cell by means of a corresponding one of the local write buffers 4, which is activated by each of the signals SEC less than 0:7 greater than . The driving amplitude of the global write buffer 2 for driving the global data line 3 is set so that the data propagation delay during the write of data in the farthest section SEC less than 0 greater than  is not less than a specific value corresponding to a write operating frequency.
By the way, since the global data line 3 driven by the global write buffer 2 is connected to the large number of local write buffers 4 and has a long signal line, its wiring resistance and wiring capacitance as well as the gate capacitance of MOS transistors have very large values. Therefore, in order to prevent the write operating frequency from lowering, the charging/discharging currents of loads must be set to be very large values, so that there is a problem in that it is not possible to avoid the increase of current consumption. This problem is not only caused particularly in semiconductor memory devices, but it is also caused in all of semiconductor devices which have large electrostatic capacity and large wiring resistance and in which gate circuits to be connected are scattered on signal lines. Particularly in recent years, with the improvement of operating frequencies and parallel processing degrees, the current consumption of semiconductor devices tends to increase, so that it is increasingly an important problem in future that how current consumption is reduced.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a buffer circuit capable of reducing its current consumption while holding its operating frequency, and a semiconductor device and semiconductor memory device using the same.
According to a first aspect of the present invention, there is provided a buffer circuit comprising:
an input terminal to receive input data;
an output terminal to output a driving signal based on said input data to an output signal line which is connected to a plurality of gate circuits; and
a driving amplitude changing circuit configured to change an amplitude of said driving signal in accordance with assignment of a specific gate circuit in said plurality of gate circuits.
According to a second aspect of the present invention, there is provided a semiconductor device comprising:
a first buffer circuit including an input terminal to receive input data, an output terminal to output a driving signal to an output signal line which is connected to a plurality of gates circuits, and a driving amplitude changing circuit configured to change an amplitude of said driving signal in accordance with assignment of a specific gate circuit in said plurality of gates;
a decoder circuit for decoding an address of said plurality of gate circuits to output a decoded signal for said plurality of gate circuits and a signal corresponding to the specific gate circuit for changing a driving amplitude to said first buffer circuit; and
a second buffer circuit configured to supply said driving signal with changed amplitude from said first buffer circuit to said specific gate circuit in response to said decoded signal from said decoder circuit.
According to a third aspect of the present invention, there is provided a semiconductor memory device comprising:
a memory cell array including a plurality of memory cells which are arranged in the form of rows and columns and each of which is provided for storing data, a plurality of bit lines which connect said memory cells in column direction and which are provided for transferring write data to said memory cells, and a plurality of word lines which are arranged in row direction and which are provided for selecting said memory cell row;
a bit line selecting circuit configured to select said bit lines on the basis of an address;
a word line selecting circuit configured to select said word lines on the basis of an address;
a data line, connected to said bit lines via said bit line selecting circuit, for transferring write data; and
a buffer circuit configured to drive said data line at an amplitude according to a position of a memory cell in which data are written.
According to the present invention, the buffer circuit is designed to change its driving amplitude in accordance with the driven gate circuit. Therefore, for example, when the signal line to the gate circuit is long, the driving amplitude is increased, and when it is short, the driving amplitude is decreased. In addition, when the gate circuit exists on a critical path, the driving amplitude is increased, and when it does not exist on the critical path, the driving amplitude is decreased. Thus, only when a path having a large signal propagation delay is driven, its driving amplitude is increased, so that it is possible to simultaneously achieve the reduction of current consumption and the improvement of the operating frequency.
According to the present invention, a buffer circuit is designed to change a driving amplitude to a data line in accordance with the position of a memory cell in which data are to be written. Therefore, when the position of the memory cell is far from the buffer circuit, the driving amplitude is increased, and when it is near to the buffer circuit, the driving amplitude is decreased, so that it is possible to achieve both of the reduction of current consumption and the improvement of the operating frequency while maintaining the operating frequency. Specifically, the buffer circuit changes its driving amplitude on the basis of, e.g., the position of a bit line and/or word line which are connected to a memory cell in which data are written. The positions of the bit lines and word lines can be distinguished by referring to at least part of an address or information obtained by decoding the address. Preferably, the buffer circuit drives the data line so that the difference between data rewriting times in memory cells connected to the same word line or the same bit line or in all of memory cells in the memory cell array is small. More preferably, memory cell arrays and buffer circuits are provided so as to make pairs, respectively, and the positions of memory cells in which data are written at the same timing are determined so that the driving amplitude of one of the buffer circuit increase when the driving amplitude of the other buffer circuit is small. Thus, the maximum value of current consumption can be suppressed.